(1) Field of the Invention
This invention relates to correction for fixed pattern noise, FPN, and more particularly to on chip correction of column based fixed pattern noise using dual column readout without the need for a large image size memory.
(2) Description of Related Art
U.S. Pat. No. 6,801,258 B1 to Pain et al. describes an imager which can be configured for multi-resolution capability where the signal to noise ratio (SNR) can be adjusted for optimum low-level detectability.
U.S. Pat. No. 6,320,616 B1 to Sauer describes methods for reducing fixed pattern noise (FTN) in complimentary metal oxide semiconductor (CMOS) image sensors.
U.S. Pat. No. 6,166,767 to Watanabe describes an active solid state imaging device which can reduce fixed pattern noise.
U.S. Pat. No. 6,128,039 to Chen et al. describes a column amplifier for high fixed pattern noise reduction.
U.S. Pat. No. 5,969,758 to Sauer et al. describe methods for correcting for DC offset and gain differences between correlated double sampling circuits of a row of correlated double sampling circuits of an imager.